FIG. 1 depicts the architecture of a non-volatile semiconductor memory array. The array of electrically erasable memory cells is composed of transistors formed by the intersection of word lines and bit lines. The drain terminals of the memory cells are coupled to the bit lines. The control gates extend across the array and are coupled to the word lines. Programming, erasure and reading of flash memory cells is accomplished by the proper application of voltage levels to cell gates, drain and sources. For example, programming a memory cell requires the application of 7 volts to the bit line, 12 volts to the word line, and 0 volts to the cell source. Erasure requires the application of 12 volts to the cell source while the cell drain and gate are allowed to float. Finally, a memory cell's contents may be read by applying 5 volts to both the word and bit lines.
One type of non-volatile semiconductor memory, flash, generally utilizes two power supplies. Vcc is typically a 5 volt supply used to power logic and Vpp is typically a 12 volt supply used to program and erase memory cells.
While the power supplies are at steady state, the application of program and erase voltage levels to memory cells is successfully controlled via logic level control signals; i.e. via control signals generated from Vcc, such as ERASE, PROGRAM and READ. Thus, during steady state operation of power supplies Vcc and Vpp, the integrity of data stored within the non-volatile semiconductor memory is guaranteed. However, the integrity of data stored within a non-volatile semiconductor memory poses a problem when power is first applied, power-up, or removed, power-down. It is possible during power-up or power-down that Vpp will be at 12 volts while Vcc is insufficient to drive the logic generating the program and erase control signals. In this situation, the integrity of memory cell contents cannot be guaranteed.
One prior method of ensuring data integrity during power-up and power-down is power supply sequencing. During power-up, Vcc is allowed to reach steady state before Vpp is applied. Similarly, during power-down Vpp is lowered below some threshold before Vcc is removed or lowered. This prior method is not infallible because it relies upon the memory user to guarantee data integrity.
One prior circuit 10 intended to help provide data integrity during power-up and power-down is shown in FIG. 2. Prior circuit 10 is used in conjunction with the control signals input to the memory array, ERASE, PROGRAM and READ, to protect data stored within the memory array.
A number of conventions are generally followed in FIG. 2. P-type transistors are drawn with a bubble on the gate, N- type transistors without the bubble. Transistors, whether P or N type, are generally drawn with their sources connected to power.
Prior circuit 10 provides an output 12, H.sub.out, which is used to control the application of program and erase voltages to memory cells. Prior circuit 10 may be used in conjunction with the source switch, row decoder or column decoder shown in FIG. 1. For example, the source switch could be controlled using H.sub.out, allowing erasure to occur while H.sub.out 12 is active at 0 volts and preventing erasure while H.sub.out 12 is 12 volts. H.sub.out 12 should be 0 volts only when both circuit inputs 14 and 16 are active. Control input 14 is a logic signal generated from the Vcc supply and is active low. In other words, control input 14 allows erasure when it is approximately 0 volts. The second input, LowVcc 16, is an analog signal indicative of the level of the Vcc supply. While Vcc is at or above some desired level, for example 4 volts, LowVcc 16 will be zero volts. So long as LowVcc 16 is zero volts, the level of H.sub.out 12 is determined by the control input. When LowVcc 16 rises above zero volts, H.sub.out 12 should ideally be approximately 12 volts, thereby preventing the erasure of memory cells.
A more detailed examination of prior circuit 10 reveals that it does not function exactly as desired; i.e., H.sub.out 12 may not always be 12 volts while LowVcc 16 is above 0 volts. Consider the operation of prior circuit 10 at a point during power-up or power-down when Vcc is not fully valid. Assume that Vcc=1 volt. Because Vcc is not fully valid, the state of any signal generated using the Vcc supply cannot be guaranteed. Thus, control input 14 may be active logic low. If control input 14 is active, a low will be input to inverter I1 18, which will output some positive voltage level to the gate of transistor N2 20. Transistor N2 20 will conduct, attempting to drive H.sub.out 12 to 0 volts. The level of H.sub.out 12 cannot be predicted because transistor P2 22 will also be conducting. Zero volts will be applied to the gate of transistor P2 22 because transistor N3 24 will be on while LowVcc 16 is above 0 volts. Because the source of transistor P2 22 is at 12 volts, P2 22 will try to drive H.sub.out 12 to 12 volts. With both transistors P2 22 and N2 20 conducting the voltage level of H.sub.out 12 could be anywhere between 0 volts and 12 volts. Thus, a circuit using prior circuit 10 for cell source protection would be in danger of accidental erasure of memory contents during power-up and power-down. Further, no data integrity scheme using prior circuit 10 will be foolproof.